A major hurdle in the gate dielectric scaling using conventionally grown SiO2 has been excessive tunneling that occurs in ultra-thin (<25Å) SiO2. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta2O5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first SiO2 (8-12Å) layer of the SiO2-Ta2O5 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on Tox. Stacked Ta2O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick Ta2O5 layer at 480°C, 300mTorr followed by an in-situ 550°C UV-03 anneal to densify the Ta2O5 film and grow an additional 5Å SiO2 layer underneath the first grown SiO2 layer resulting in an effective SiO2 thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown SiO2 layer resulting in an effective SiO2 thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements.