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Visualizing Sub-Micron Burried Metal Line in VLSI Devices using a SEM
Published online by Cambridge University Press: 02 July 2020
Extract
In recent years, the critical dimension in “Very Large Scale Integrated” devices has dramatically decreased. The microelectronics industry road map predicts that by the year 2000 the critical dimension will be below 250 nm. This reduction in scale will imply the development of new techniques to control the fabrication of such devices. This paper presents a novel approach to characterize VLSI devices based on Monte Carlo calculations. The principle of this technique is to use information from backscattered electrons (BE). The energies of those electrons are related to their maximum range within the structure. Thus it is possible to distinguish the layer from which they are backscattered. In order to collect this information an energy filtered backscattered electron detector must be used.
Figure 1 shows a cross section of a structure produces using a typical VLSI process. The two metal layers are usually patterned to define small lines and contacts.
- Type
- Recent Developments in Microscopy for Studying Electronic and Magnetic Materials
- Information
- Microscopy and Microanalysis , Volume 3 , Issue S2: Proceedings: Microscopy & Microanalysis '97, Microscopy Society of America 55th Annual Meeting, Microbeam Analysis Society 31st Annual Meeting, Histochemical Society 48th Annual Meeting, Cleveland, Ohio, August 10-14, 1997 , August 1997 , pp. 499 - 500
- Copyright
- Copyright © Microscopy Society of America 1997