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Strain Field Distribution in Submicron Devices by TEM/CBED. A European Project

Published online by Cambridge University Press:  02 July 2020

A Armigliato
Affiliation:
CNR-Istituto LAMEL, via P.Gobetti, 101, 40129, Bologna, Italy
R Balboni
Affiliation:
CNR-Istituto LAMEL, via P.Gobetti, 101, 40129, Bologna, Italy
G P Carnevale
Affiliation:
ST Microelectronics s.r.l., via C.Olivetti, 2, 20041, Agrate, Brianza(, Italy)
P Colpani
Affiliation:
ST Microelectronics s.r.l., via C.Olivetti, 2, 20041, Agrate, Brianza(, Italy)
S Frabboni
Affiliation:
INFM and Dipartimento di Fisica, Universita di Modena e Reggio Emilia, via Campi 213/A, 41100, Modena, Italy
G Pavia
Affiliation:
ST Microelectronics s.r.l., via C.Olivetti, 2, 20041, Agrate, Brianza(, Italy)
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Extract

It is now widely accepted that one of the major issues for the future deep sub-micron integrated circuit (IC) technologies regarding yield, device performance and stability and device and product reliability, is the mechanical stress built up in the layers and substrate. It is therefore important to give a quantitative account of these stresses and this can only be achieved by disposing of reliable, performant (as to spatial resolution) and quantitative techniques for the local stress determination in the substrate, of adequate and dedicated process simulation tools and of sensitive methods to analyse the stress effects on device performance.

The only experimental technique presently available which allows the strain field distribution in sub-micron CMOS devices is the convergent beam electron diffraction technique of the transmission electron microscopy. Its sensitivity is of the order of 10-4 and its spatial resolution is of 1 nm if a TEM/FEG is employed.

Type
Semiconductors
Copyright
Copyright © Microscopy Society of America

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References

References:

1.Armigliato, A. et al., Proc. Microsc. Semicond. Mater. Conf., Inst. Phys. Conf. Ser. No. 164 (1999) 447Google Scholar
2.Armigliato, A. et al., Micron (1999) in pressGoogle Scholar
3. STREAM: Stress minimisation on deep sub-micron CMOS processes, measured by a high spatial resolution technique, and its application to 0.15 micron non volatile memories (Contract Number 1ST-1999-10341)Google Scholar