Failure analysis in the microelectronic industry via TEM has long dealt with the specimen preparation spatial resolution problem—the ability to prepare useful TEM specimens at very small pre-selected locations. This problem is made more difficult with time because, while device structures become smaller and more dense, the failure rate of individual devices is extremely low and dropping. TEM analysts, therefore, must prepare specimens that optimally present a single faulty component within an ocean of a billion or more similar components. Sophisticated electrical testers can find the faulty component and transfer its coordinates to a FIB tool where the failure can be marked. Cross section TEM specimens are appropriate when it is suspected that the failure is caused by a defect in the stack of metal and insulators constructed on the top of the device substrate (usually silicon). Plan view TEM specimens are appropriate when the electrical signature of the failure indicates that the fault lies in the Si itself-dislocations or some other crystal defect.