Interfacial dislocations (IDs) and half-loop arrays (HLAs) present in theepilayers of 4H-SiC crystal are known to have a deleterious effect on deviceperformance. Synchrotron X-ray Topography studies carried out on n-type 4H-SiCoffcut wafers before and after epitaxial growth show that in many cases BPDsegments in the substrate are responsible for creating IDs and HLAs during CVDgrowth. This paper reviews the behaviors of BPDs in the substrate during theepitaxial growth in different cases: (1) screw-oriented BPD segmentsintersecting the surface replicate directly through the interface during theepitaxial growth and take part in stress relaxation process by creating IDs andHLAs (Matthews-Blakeslee model [1] ); (2) non-screw oriented BPD half loopintersecting the surface glides towards and replicates through the interface,while the intersection points convert to threading edge dislocations (TEDs) andpin the half loop, leaving straight screw segments in the epilayer and thencreate IDs and HLAs; (3) edge oriented short BPD segments well below the surfaceget dragged towards the interface during epitaxial growth, leaving two longscrew segments in their wake, some of which replicate through the interface andcreate IDs and HLAs. The driving force for the BPDs to glide toward theinterface is thermal stress and driving force for the relaxation process tooccur is the lattice parameter difference at growth temperature which resultsfrom the doping concentration difference between the substrate and epilayer.