The extended defects, such as dislocations and in-grown stacking faults (IGSFs), in 4H-SiC epilayers have been detected and visualized by a non-destructive method, the micro photoluminescence (μ-PL) intensity mapping method, at room temperature. The one-to-one correspondence between the extended defects and the μ-PL mapping contrast has been successfully obtained. A threading dislocation corresponds to a dark circle with the reduced intensity in the μ-PL mapping image performed at 390 nm, while a basal plane dislocation dissociates into a single Shockley SF during the measurements. Three kinds of IGSFs have been identified in the samples. Each kind of IGSF shows the distinct PL emission located at 460 nm, 480 nm, and 500 nm, respectively. The shapes and distributions of IGSFs have also been profiled by μ-PL intensity mapping.

In this work, the mechanical properties of cubic silicon carbide are explored through the analysis of the static and dynamic behavior of 3C-SiC cantilevers. The investigated structures were micro-machined using Inductively Coupled Plasma (ICP) etching of thin 3C-SiC films grown on silicon. The aim was to evaluate the influence of some basic parameters (film orientation, film thickness, defect density) on the mechanical properties of the material.

X-Ray Diffraction was used to evaluate the crystalline quality of the epilayers. Scanning Electron Microscopy observations of static cantilever deflection highlight the major difference between the stress states of (100) and (111) oriented layers for which the intrinsic stresses are of opposite signs. The cantilever deflection is highly dependent on the film thickness, as stated for (100) oriented epilayers. The lowest deflection is obtained for the thickest layer. The Young's modulus of 3C-SiC is calculated from the resonance frequency of clamped-free cantilevers, measured by laser Doppler vibrometry. The relatively low and orientation independent value of Young's modulus (~350GPa) found on the samples is probably associated with the high defect density usually observed in very thin 3C-SiC films grown on Si.

Silicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO2) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.

Silicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.

For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.

The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.

In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.

Three dimensional kinetic Monte Carlo simulations on super-lattices are applied to study the evolution of stacking faults during epitaxial growths. We show that, in the case of misoriented close packed substrates, these defects can either extend throughout the entire epilayer (i.e. extended from the substrate up to the surface) or close in dislocation loops, in dependence of the deposition conditions. We explain this behavior in terms of a surface kinetic competition between these defects and the surrounding crystal: if the local growth rate of the defect is larger compared with that of the perfect crystal the defect will expands, otherwise it will closes. This mechanisms allows to explain several experimental results on homo and hetero epitaxies.

Shockley-type Stacking faults (SSF) in hexagonal Silicon Carbide polytypes have received considerable attention in recent years since it has been found that these defects are responsible for the degradation of forward I-V characteristics in p-i-n diodes. In order to extend the knowledge on these kind of defects and theoretically support experimental findings (specifically, photoluminescence spectral analysis), we have determined the Kohn-Sham electronic band structures, along the closed path Γ-M-K-Γ, using density functional theory. We have also determined the energies of the SSFs with respect to the perfect crystal finding that the (35) and (44) SSFs have unexpectedly low formation energies, for this reason we could expect these two defects to be easily generated/expanded either during the growth or post-growth process steps.

Cubic 3C-SiC is regarded as a perfect material for medium power MOSFETs with blocking voltages of around 1500V and current handling of 100A and more. One of the main issues to realize such power MOSFETs is the improvement of the MOS gate to ensure low on-state resistance operation.

The benefits of the implementation of an advanced oxidation process combining PECVD SiO2 deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [1]. The concentrations of fixed and mobile charges in the oxide and at the SiO2/SiC interface were significantly reduced. But the optimization of the gate material is still an issue.

The experiences from silicon technology point in the direction of using a poly-Si gate for MOS controlled devices. Significant improvements in terms of gate oxide reliability could be achieved by applying a poly-Si gate. But the usage of hydrogen for passivation of defects in oxides grown on 3C-SiC gives restrictions to the poly-Si deposition and activation process conditions. A reduced thermal budget is required to preserve the high electrical properties of the oxide.

We investigated the electrical properties of MOS structures prepared with poly-Si gates. The poly-Si layer was deposited by the LPCVD technique mixing Si2H6 and PH3 at 380°C. The poly-Si activation has been carried out with five different methods. The influence of the following two main parameters has been considered: the process duration (thermal annealing or rapid thermal annealing) and the gas atmosphere (argon, dry or wet oxygen).

MOS capacitors were fabricated on the oxidized free-standing n-type 3C-SiC (001) wafers with 5μm low nitrogen doped (5×1015 cm-3) epitaxial layers. The MOS capacitors were characterized on the wafer level (about 200 MOS structures per wafer) by capacitance-conductance-voltage (C-G-V) measurements using a HP4284A LCR meter in the frequency range of 100 Hz to 1 MHz. The measurements were performed at room temperature in a light-tight and electrically shielded environment. The interface trap densities Dit were extracted by the conductance method. To assess the oxide reliability, time-zero dielectric breakdown (TZDB) measurements were conducted on the fabricated MOS structures.

The optimized poly-Si activation process based on RTA in argon has minimal thermal budget and preserves the oxide and interface quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide: A small negative flat band voltage shift of -1V and an interface state density Dit of 7.4×1010 eV-1cm-2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.

Phosphorus is an important n-type dopant for both silicon and silicon carbide. Although solid-state diffusion of phosphorus in silicon has been well documented and experimentally proven, not much is known about phosphorus solid-state diffusion in silicon carbide, especially at lower temperatures. A convenient source of phosphorus for solid-state diffusion in silicon carbide is phosphorus oxide. The possibility of using phosphorus oxide as a dopant source for silicon carbide is investigated by considering the probable reactions between silicon carbide and phosphorus oxide at temperatures below 1700 K using published thermodynamic data. By considering the standard free energies of reactions, it can be shown that phosphorus can be introduced in silicon carbide at temperatures below 1700 K using phosphorus oxide. A successful development of low temperature dopant incorporation in silicon carbide would reduce the need for high temperature processes and prevent process-induced thermal degradation of critical device structures such as the oxide-semiconductor interface. Experimental results showing phosphorus impurity incorporation and activation in 4H-SiC are presented.

Epitaxial 3C-SiC was grown using an unconventional technique for epitaxial growth. Thin films of 3C-SiC were deposited onto the (111) and (110) faces of Si using pulsed DC sputtering of a high purity, hollow cathode SiC target. The films were studied using x-ray diffraction (XRD), reflection high energy electron diffraction (RHEED), transmission electron microscopy (TEM), and auger electron spectroscopy (AES) techniques. XRD results presented as Bragg diffraction spectra and pole figures, and electron diffraction patterns verify crystal orientation and epitaxy. In addition, AES profiles identify the compositional integrity of the deposited films.

In this paper we present results on the use of a multilayered a-SiC:H heterostructure as a wavelength-division demultiplexing device (WDM) for the visible light spectrum. The WDM device is a glass/ITO/a-SiC:H (p-i-n)/ a-SiC:H(-p) /Si:H(-i)/SiC:H (-n)/ITO heterostructure in which the generated photocurrent at different values of the applied bias can be assigned to the different optical signals.

The device was characterized through spectral response measurements, under different electrical bias. Demonstration of the device functionality for WDM applications was done with three different input channels covering wavelengths within the visible range. The recovery of the input channels is explained using the photocurrent spectral dependence on the applied voltage. The influence of the optical power density was also analysed.

An electrical model, supported by a numerical simulation explains the device operation. Short range optical communications constitute the major application field, however other applications are also foreseen.

4H SiC is a promising material because of its mechanical, electrical, and physical properties. However, SiC material defects have had a rate limiting effect on the widespread adoption of SiC. Micropipes, basal plane dislocations (BPD), elementary screw dislocations (SDD) and threading edge dislocations (TED) have all been identified as limiting to device operation and/or performance. An ideal PVT strategy for manufacturing SiC crystals would be capable of driving defects out the crystal via a combination of thermal field control and defect dissociation pathways. In this work a PVT technology was realized which is capable of continuously improving the crystal quality. A low defect PVT process was conceived and optimized using iterative experiment and simulation methods. During the maturation of the process it was observed that the crystal defect density repeatedly decreased relative to the seed crystal, as evaluated by x-ray topography, x-ray diffraction, and molten salt etching. The process improvements were leveraged successfully to achieve 4H n+ SiC wafers at 76-100 mm diameter with MPD <1 cm-2, SDD <500 cm-2, and BPD <500 cm-2. This paper will illustrate the defect reduction pathways leading to state of the art defect density 4H SiC crystals and the impact of the improved crystal on epitaxy defects and simple device experiments.

An analytical study of the dependence of shear and von-Mises stress distributions, which develop during PVT (Physical Vapor Transport) growth of 4H-SiC, has been executed. The key parameters investigated include thermal conditions of the crystal growth and parameters of the growing boule geometry. The evaluation was conducted via a 24 full factorial DOE (Design of Experiments). Parameters of the growing boule geometry, i.e. seed diameter, growth front height, inclination angle and height of the side surface were set as the DOE factors, while responses were calculated using numerical simulations. It is found that unique SiC boule growth conditions, which simultaneously minimize both the shear stress and von Mises stress magnitudes, cannot be achieved. Optimization of the shear stress distribution favors longer SiC boules with small seed diameters, small expansion angles and flat growth fronts. Alternatively, optimization of von-Mises stress favors short crystals with small seed diameters and small expansion angles but with curved growth fronts. Consequently, optimization of stress components in SiC crystals involves careful investigation of the interaction and compromise of the reaction cell geometry and growth conditions.