In this paper, we have performed further investigations and deepened our understanding of Polymer Resistive Random Access Memory devices (PoRRAM) on silicon substrate. Organic thin films based on blend of fullerene (C60) molecules and poly-methyl-methacrylate resist (PMMA) were analyzed from a material and electrical point of views. We have enlightened first the necessity of thermal treatment on the nano-composite layer in order to obtain memory effect in the device. Indeed from I-V measurements, only devices that had a thermal activation exhibited the hysteresis phenomenon, characteristic of the memory effect. The impact of thermal annealing has been investigated by morphological analysis (AFM and confocal microscopy) before and after thermal treatment. This process step induced the C60 molecules aggregation in the polymer matrix. The morphological study of these aggregates coupled with electrical measurements allowed us to determine the influence of aggregation on the electrical behavior. Due to their flexibility, this organic memories based on PMMA:C60 nanocomposites show a strong potential for an adaptation on plastic substrate.

The nanocrystalline molybdenum oxide embedded Zr-doped HfO2 high-k nonvolatile memory device has been fabricated using the one pumpdown sputtering process and a rapid thermal annealing step. The majority embedded molybdenum existed in the MoO3 nanocrystal form but a small amount of metallic molybdenum was also detected. The memory function of this device was based on the hole trapping-and-detrapping mechanism. The embedded nanocrystals retained charges after the breakdown of the high-k stack. The charge storage capacity was influenced by light exposure, especially the wavelength. The silicon/high-k interface was also affected by the exposed light. This study provided an insight of the function of the embedded nanocrystals and the light effects on the device.

Metal/high-k dielectric core-shell nanocrystal (NC) memory capacitors were demonstrated by e-beam evaporation process. This kind of metal oxide semiconductor (MOS) memory shows good performance in charge storage, programming and erasing speeds. Compared to Co NC memory, Co/Al2O3 core-shell NC memory shows improved retention performance since the additional Al2O3 shell layer acts as a barrier, which prevent the leakage.

In this work we examine the development of ion beam modified oxide-nitride-oxide structures formed by low-energy (1 keV) implantation of Si, N and Ar ions (1x1016 ions/cm2) into oxide-nitride gate stacks and subsequent wet-oxidation to form the blocking oxide. Transmission electron microscopy indicates that the thickness of the blocking oxide layer is strongly affected by the implantation process going from 1 nm (non-implanted sample) to 4-5 nm (N and Ar implants) and 7.5 nm (Si implant). The Si implanted stacks exhibit the highest attainable memory window (∼ 8.5 V for a 1 ms pulse regime), which involve both electron and hole storage. In contrast the thinner blocking oxide that develops to the nitrogen and argon implanted stacks limits the memory window which is due only to electron trapping. Room temperature charge retention measurements of the programming state reveal that the electron loss rate is faster in samples implanted with Si than N, allowing for a memory window of 1.7 V and 2.5 V respectively after ten years extrapolation. This retention behavior is mainly attributed to the different nature of the traps generated in the implanted materials.

Gapless-type atomic switches were fabricated on a flexible plastic substrate by printing ‘solid polymer electrolyte’ (SPE) layers using suitable ink and drop-on-demand ink-jet technique. High surface energy difference between Pt microelectrode patterned on the plastic substrate and the substrate itself, led to the successful printing of electrolytic solution on a bottom Pt electrodes. Bipolar resistive switching behavior was observed in Ag/SPE/Pt cross-point structures under electrical bias. The switching between ON and OFF states is attributed to the formation and dissolution of a metal filament between the electrodes. The cells also exhibited stable switching behavior under mechanical stress as performed by substrate bending. Switching characteristics measured under mechanical stress and without stress are matching well. The results demonstrate that the SPE-printed atomic switch has great potential for flexible switch/memory applications.

We fabricated Fe3O4 thin films on TiN buffered Si by CO/CO2 oxidation at 160 °C. The easy saturation of the magnetization at high magnetic field and high resolution scanning transmission electron microscopy (HRSTEM) images show low defect density, smooth Fe3O4 thin films. Oxidation at 400 °C resulted in an undesirable second phase in between the TiN and the un-oxidized Fe, but changes in total gas pressure did not lead to a second phase. The crystal structure of this second phase is similar to Fe2TiO4 (ulvöspinel) from HRSTEM and STEM electron energy loss spectroscopy. Fe3O4 thin films grown at 160 °C follow a power law growth model with an exponent of 0.23±0.03.

The electronic transport properties of the organic ferroelectric gate field-effect transistors (FeFETs) with the ZnO channel were investigated. The FeFETs with the channel thickness below 100 nm show nonvolatile operation and the on/off ratio of 105. The field-effect mobility decreased with decreasing the channel thickness. From the Hall-effect measurement, it was found that the Hall mobility increases and the carrier concentration decreases after the deposition of the organic ferroelectric gate. From these results, the effect of the ferroelectric polarization on the electronic transport in the FeFETs was discussed.

We report a study of resistive switching in a silicon-based memristor/resistive RAM (RRAM) device in which the active layer is silicon-rich silica. The resistive switching phenomenon is an intrinsic property of the silicon-rich oxide layer and does not depend on the diffusion of metallic ions to form conductive paths. Both unipolar and bipolar programming is demonstrated.

Switching exhibits the pinched hysteresis I/V loop characteristic of RRAM/memristive systems, and on/off resistance ratios of 104:1 or higher can be easily achieved. Scanning Tunnelling Microscopy suggests that switchable conductive pathways are 10nm in diameter or smaller.

We report on the materials issues involved in the hybrid floating gate (HFG) device fabrication, where the interpoly dielectric is replaced by an intermetal dielectric (IMD). Indeed, in HFG the dielectric is inserted in between two metal layers in a metal\dielectric\metal stack. The materials of choice were TiN as the metal layer and Al2O3 and HfO2 (and their combination) as IMD. The program/erase performance is discussed based on the dielectric constant and crystallinity of the IMD and the metal-IMD interface characteristics.

The typical architectures for single-transistor capacitorless dynamic random access memory (1T-DRAM) are reviewed. This memory takes advantage of floating-body effects in SOI-like devices. The principles of operation and the key mechanisms for memory programming and reading are described. Most of these devices can be enriched with non-volatile storage capability. Several possibilities for such ‘unified’ memory are explored.