Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Joel Barnett; N. Moumen; J. Gutt; M. Gardner; C. Huffman; P. Majhi; J.J. Peterson; S. Gopalan; B. Foran; H.-J. Li; B.H. Lee; G. Bersuker; P. M. Zeitzoff; G.A. Brown; P. Lysaght; C. Young; R.W. Murto; H. R. Huff

doi:10.1557/PROC-811-E1.4

Abstract

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

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Article contents

Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Abstract

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This article has been cited by the following publications. This list is generated based on data provided by Crossref.

Article contents

Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Abstract

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References

REFERENCES

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